The subject matter disclosed herein generally relates to clock-gating and, more particularly, to clock-gating for multicycle instructions.
Modern processor designs can contain millions of latches. These latches are carefully gated and controlled at least in part because of power and heat considerations. For example, if all the latches in a modern processor were clocked every cycle the processor chip would likely fail from heat and strain or need to run at much lower frequency. If the chip could sustain such clocking the power consumption would be immense and the heat dissipation system and structure necessary would need to be large and complex. Further, constant clocking of the latches may shorten the life of the processor by increasing the rate of degradation of the circuit latches.
Thus, clock gating is important to achieving the thermal design power (TDP) which is the maximum amount of heat generated by a computer chip or component that the cooling system in a computer is designed to dissipate in typical operation. While pipelined instructions can be relatively easily clock-gated by activating the cycles of the pipeline one at time as the instruction transition thru the stages, other accesses or multicycle instructions present with a number of challenges that make it difficult to clock-gate. For example, existing pre-indicators marking which stages of the pipeline to activate and for how many cycles the pipeline stage should be active do not exist or are very imprecise for other accesses and/or multicycle instructions. Further, a local detection is complex and happens only very late. This causes a significant block of logic, many thousands of latches, being constantly clocked as soon as e.g. an instruction or an imprecise pre-indicator event is detected. Thus, because the clocking for multicycle operations is not gated, this clocking is run permanently causing unnecessary power consumption and heating. This consumption of considerable energy as well as heat dissipation resources are therefore consumed and therefore cannot be used for additional logic that would increase performance.
Accordingly, there is a desire to provide a system and/or method for handling clock-gating for multicycle instructions.